YosysHQ/yosys
Yosys Open SYnthesis Suite
About the project
Yosys is an open-source RTL synthesis framework supporting Verilog-2005 and a synthesizable subset of SystemVerilog. It converts HDL descriptions into netlists and optimizes digital logic.
Useful for
- Synthesize a Verilog project into a netlist for FPGA implementation.
- Run formal verification of an HDL design using SBY.
- Extend Yosys with custom synthesis passes in C++.
README summarized by DeepSeek V4.1 Flash. Details may be inaccurate.
Why it’s trending
- 3 stars today.
Stars per day
Bars are daily stars, the line is the usual pace. Red marks spike days.
Numbers
- Total stars
- 4,752
- Stars in a day
- 3
- Forks
- 1,160
- Issues and pull requests
- 5,902
- Watchers
- 130
- Language
- C++
- License
- ISC
- Latest release
- v0.69 · September 9, 2026
- Created
- January 5, 2013
- Last push
- September 11, 2026
Star trust
Growth looks organic: forks and discussion are in line with active projects, and stars arrive unevenly, the way people give them.
These are heuristics, not a verdict: we judge by the repository’s behavior, not by a list of stargazers.
Spotted in
- September 13, 2026GitHub Trending C++ today: #19, +1 star
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